Half-bridges are used to convert direct current (DC) to DC, DC to alternating current (AC), or AC to DC. Switching at higher frequencies enables small, cheaper passive components. For large switches, parasitic inductances and gate resistance slow turn-on time, as illustrated in FIG. 1, which shows a GaN HFET switching on 20 A at 350V.
Inductance in the power loop of a half-bridge slows the current switching time, τI, as approximated by Equation 1, below, by reducing the gate voltage by ΔVgs. Gate resistance slows the voltage switching time, τv, as approximated by Equation 2, below. Id and Qgd increase in proportion to switch power, but the parasitic source inductances, Ls, and gate resistance, Rg, do not reduce in proportion, and consequently large switches have slower turn-on times and are less efficient at high switching frequencies. The positive gate-source voltage, Vg+, and the plateau voltage, Vplat, in general do not change with switch size.
                              τ          I                =                              L            s                    ·                                    Δ              ⁢                                                          ⁢                              I                d                                                    Δ              ⁢                                                          ⁢                              V                gs                                                                        (        1        )                                          τ          V                =                                            Q              gd                        ·                          R              g                                            (                                          V                                  g                  +                                            +                              V                plat                                      )                                              (        2        )            
A lateral 20 A GaN HFET switch may have 6 cells in parallel, each with 72 1 mm wide fingers in parallel. In such a design the gate resistance, Rg, of the 20 A switch is dominated by the gate feed resistance. Table 1 shows the estimated turn-on times for GaN HFETs of different sizes and types.
Rg *Ron *GateAreaAreawidthRgQgdtonRonAreaohms-ohm-TypemmohmsnCnsohmsmm2mm2mm21 cell201.0 0.7 1.21.000 1.81.81.81 cell400.8 1.3 2.00.500 3.22.61.66 cell4320.414.016.00.04564.025.62.9102000.1 7.0 2.90.10017.81.81.8parallel
In a multi-cell design, the power loop inductance and the switched current increases voltage overshoot. FIG. 2 shows the turn-off of a GaN HFET switching 20 A at 350V resulting in a 150V overshoot from power loop inductance of ˜12 nH. Overshoot voltage may damage switches or require switches of a higher voltage rating, which would increase the on resistance (Ron). High on-resistance results in higher conduction loss and decreased converter efficiency. The on resistance (Ron) generally increases in proportion to the square of the voltage rating of the switch.
Gate inductance also slows switching and causes ringing. Ringing of the gate voltage can result in high overshoot voltage, which can damage the switches. The intrinsic gate inductance of a lateral switch increases with switch size, along with the gate capacitance. It is challenging to reduce external wire bond gate inductance inversely proportionally to the switch size. The problem of ringing caused by gate inductance and switch capacitance increases with switch size.
As a lateral switch increases in size, the contribution to Ron from feed resistance increases rapidly. Device metallization thickness and sheet resistance is usually limited by constraints of the lithographic processes. Wider feed traces, to prevent feed resistance from dominating Ron, increase switch area, increase Ron*A, and increase switch cost. Table 1 above shows the increase of Ron*Area for the 6 cell design with a gate width of 432 mm compared to the single cell or paralleled switches.
Prior art half bridge switches generally used silicon. When higher speed technologies, such as GaN, the switching times are at least 5 times faster, and the above issues are exacerbated.
Finally switch yield of an immature switch technology decreases rapidly with switch size. The yield of small switches can be high, but for large size switches the yield is quite low.
What is needed is a half bridge device that addresses the above problems in the prior art. A half bridge device is desired that reduces source inductance, gate resistance, looping inductance, while increasing switch yield. The embodiments of the present disclosure answer these and other needs.